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eroflex circuit technology - advanced multichip modules ? scd1668 rev a 4/28/98 circuit technology www.aeroflex.com general description the act?f512k8 is a high speed, 4 megabit cmos monolithic flash module designed for full temperature range military, space, or high reliability applications. this device is input ttl and output cmos compatible. the command register is written by bringing we to a logic low level (v i l ), while ce is low and oe is at logic high level (v i h ) . reading is accomplished by chip enable ( ce ) and output enable ( oe ) being logically active, see figure9. access time grades of 60ns, 70ns, 90ns, 120ns and 150ns maximum are standard. the act?f512k8 is available in a choice of features n low power monolithic 512k x 8 flash n ttl compatible inputs and cmos outputs n access times of 60, 70, 90, 120 and 150ns n +5v programing, 5v 10% supply n 100,000 erase / program cycles n low standby current n page program operation and internal program control time n supports full chip erase n embedded erase and program algorithms n supports full chip erase n mil-prf-38534 compliant circuits available n industry standard pinouts n packaging ? hermetic ceramic l 32 lead, 1.6" x .6" x .20" dual-in-line package (dip), aeroflex code# "p4" l 32 lead, .82" x .41" x .11" ceramic flat package (fp), aeroflex code# "f6" l 32 lead, .82" x .41" x .132" ceramic flat package (fp lead formed), aeroflex code# "f7" n sector architecture l 8 equal size sectors of 64k bytes each l any combination of sectors c can be erased with one command sequence. n commercial, industrial and military temperature ranges n desc smd pending 5962-96692 (p4,f6,f7) block diagram ? dip (p4) & flat packages (f6,f7) 512kx8 oe a 0 ? a 18 i/o 0-7 8 we ce vss vcc pin description i/o 0-7 data i/o a 0?18 address inputs we write enable ce chip enable oe output enable v c c power supply v s s ground nc not connected act?f512k8 high speed 4 megabit monolithic flash
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 2 hermetically sealed ceramic packages; a 32 lead .82" x .41" x .11"flat package in both formed or unformed leads or a 32 pin 1.6"x.60" x.20" dip package for operation over the temperature range -55c to +125c and military environmental conditions. the flash memory is organized as 512kx8 bits and is designed to be programmed in-system with the standard system 5.0v vcc supply. a 12.0v v p p is not required for write or erase operations. the device can also be reprogrammed with standard eprom programmers (with the proper socket). the standard act?f512k8 offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the device has separate chip enable ( ce ), write enable ( we ) and output enable ( oe ) controls. the act?f512k8 is command set compatible with jedec standard 1 mbit eeproms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 12.0v flash or eprom devices. the act?f512k8 is programmed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. typically, each sector can be programmed and verified in less than 0.3 second. erase is accomplished by executing the erase command sequence. this will invoke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the device is typically erased and verified in 1.5 seconds (if already completely preprogrammed). also the device features a sector erase architecture. the sector mode allows for 64k byte blocks of memory to be erased and reprogrammed without affecting other blocks. the act-f512k8 is erased when shipped from the factory. the device features single 5.0v power supply operation for both read and write functions. lnternally generated and regulated voltages are provided for the program and erase operations. a low v c c detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of d 7 or by the toggle bit feature on d 6 . once the end of a program or erase cycle has been completed, the device internally resets to the read mode. all bits of each die, or all bits within a sector of a die, are erased via fowler-nordhiem tunneling. bytes are programmed one byte at a time by hot electron injection. a desc standard military drawing (smd) number is pending. general description, cont?d ,
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 3 z absolute maximum ratings parameter symbol range units case operating temperature t c -55 to +125 c storage temperature range t s t g -65 to +150 c supply voltage range v c c -2.0 to +7.0 v signal voltage range (any pin except a 9 ) note 1 v g -2.0 to +7.0 v maximum lead temperature (10 seconds) 300 c data retention 10 years endurance (write/erase cycles) 100,000 minimum a 9 voltage for sector protect, note 2 v i d -2.0 to +14.0 v note 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, inputs may undershoot v s s to -2.0v for periods of up to 20ns. maximum dc voltage on input and i/o pins is v c c + 0.5v. during voltage transitions, inputs and i/o pins may overshoot to v c c + 2.0v for periods up to 20 ns. note 2. minimum dc input voltage on a 9 is -0.5v. during voltage transitions, a9 may undershoot v s s to -2.0v for periods of up to 20ns. maximum dc input voltage on a 9 is +12.5v which may overshoot to 14.0v for periods up to 20ns. normal operating conditions symbol parameter minimum maximum units v c c power supply voltage +4.5 +5.5 v v i h input high voltage +2.0 v cc + 0.5 v v i l input low voltage -0.5 +0.8 v tc operating temperature (military) -55 +125 c v i d a 9 voltage for sector protect 11.5 12.5 v capacitance (v i n = 0v, f = 1mhz, tc = 25c) symbol parameter maximum units c a d a 0 ? a 18 capacitance 15 pf c o e oe capacitance 15 pf c w e write enable capacitance 15 pf c c e chip enable capacitance 15 pf c i / o i/o 0 ? i/o 7 capacitance 15 pf parameters guaranteed but not tested dc characteristics ? cmos compatible (vcc = 5.0v, vss = 0v, tc = -55c to +125c, unless otherwise indicated) parameter sym conditions speeds 60, 70, 90, 120 & 150ns minimum maximum units input leakage current i l i v c c = 5.5v, v i n = gnd to v c c 10 a output leakage current i l o x 32 v c c = 5.5v, v i n = gnd to v c c 10 a active operating supply current for read (1) i c c 1 ce = v i l , oe = v i h , f = 5mhz 50 ma active operating supply current for program or erase (2) i c c 2 ce = v i l , oe = v i h 60 ma operating standby supply current i c c 3 v c c = 5.5v, c e = v i h , f = 5mhz 1.6 ma output low voltage v o l i o l = +8.0 ma, v c c = 4.5v 0.45 v output high voltage v o h i o h = ?2.5 ma, v c c = 4.5v 0.85 x v c c v low power supply lock-out voltage (4) v l k o 3.2 v note 1. the icc current listed includes both the dc operating current and the frequency dependent component (at 6 mhz). the freq uency component typically is less than 2 ma/mhz, with oe at v i n . note 2. icc active while embedded algorithm (program or erase) is in progress. note 3. dc test conditions: v i l = 0.3v, v i h = v c c - 0.3v, unless otherwise indicated. note 4. parameter guaranteed by design, but not tested.
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 4 ac characteristics ? read only operations (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units read cycle time t a v a v t r c 60 70 90 120 150 ns address access time t a v q v t a c c 60 70 90 120 150 ns chip enable access time t e l q v t c e 60 70 90 120 150 ns output enable to output valid t g l q v t o e 30 35 35 50 55 ns chip enable to output high z (1) t e h q z t d f 20 20 20 30 35 ns output enable high to output high z(1) t g h q z t d f 20 20 20 30 35 ns output hold from address, ce or oe change, whichever is first t a x q x t o h 0 0 0 0 0 ns note 1. guaranteed by design, but not tested ac characteristics ? write/erase/program operations, we controlled (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units write cycle time t a v a c t w c 60 70 90 120 150 ns chip enable setup time t e l w l t c e 0 0 0 0 0 ns write enable pulse width t w l w h t w p 40 45 45 50 50 ns address setup time t a v w l t a s 0 0 0 0 0 ns data setup time t d v w h t d s 40 45 45 50 50 ns data hold time t w h d x t d h 0 0 0 0 0 ns address hold time t w l a x t a h 45 45 45 50 50 ns write enable pulse width high t w h w l t w p h 20 20 20 20 20 ns duration of byte programming operation typ = 16 s t w h w h 1 14 typ 14 typ 14 typ 14 typ 14 typ s sector erase time t w h w h 2 30 30 30 30 30 sec read recovery time before write t g h w l 0 0 0 0 0 s vcc setup time t v c e 50 50 50 50 50 s chip programming time 50 50 50 50 50 sec chip erase time t w h w h 3 120 120 120 120 120 sec ac characteristics ? write/erase/program operations, ce controlled (vcc = 5.0v, vss = 0v, tc = -55c to +125c) parameter symbol jedec stand?d ?60 min max ?70 min max ?90 min max ?120 min max ?150 min max units write cycle time t a v a c t w c 60 70 90 120 150 ns write enable setup time t w l e l t w s 0 0 0 0 0 ns chip enable pulse width t e l e h t c p 40 45 45 50 55 ns address setup time t a v e l t a s 0 0 0 0 0 ns data setup time t d v e h t d s 40 45 45 50 55 ns data hold time t e h d x t d h 0 0 0 0 0 ns address hold time t e l a x t a h 45 45 45 50 55 ns chip select pulse width high t e h e l t c p h 20 20 20 20 20 ns duration of byte programming t w h w h 1 14 typ 14 typ 14 typ 14 typ 14 typ s sector erase time t w h w h 2 30 30 30 30 30 sec read recovery time t g h e l 0 0 0 0 0 ns chip programming time 50 50 50 50 50 sec chip erase time t w h w h 3 120 120 120 120 120 sec
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 5 device operation the act?f512k8 monolithic is composed of one, four megabit flash device. programming of the act?f512k8 is accomplished by executing the program command sequence. the program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell status. sectors can be pro- gramed and verified in less than 1 second. erase is accomplished by executing the erase command sequence. the erase algorithm, which is internal, auto- matically preprograms the array if it is not already pro- gramed before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell status. the entire mem- ory is typically erased and verified in 1.5 seconds (if pre-programmed). the sector mode allows for 64k byte blocks of memory to be erased and reprogrammed with- out affecting other blocks. bus operation read the act?f512k8 has two control functions, both of which must be logically active, to obtain data at the out- puts. chip enable ( ce ) is the power control and should be used for device selection. output-enable ( oe ) is the output control and should be used to gate data to the output pins of the chip selected. figure 7 illustrates ac read timing waveforms. output disable with output-enable at a logic high level (v i h ), output from the device is disabled. output pins are placed in a high impedance state. standby mode the act-f512k8 standby mode consumes less than 6.5 ma. in the standby mode the outputs are in a high impedance state, independent of the oe input. if the device is deselected during erasure or programming, the device will draw active current until the operation is com- pleted. write device erasure and programming are accomplished via the command register. the contents of the register serve as input to the internal state machine. the state machine outputs dictate the function of the device. the command register itself does not occupy an addres- sable memory location. the register is a latch used to store the command, along with address and data infor- mation needed to execute the command. the command register is written by bringing we to a logic low level (v i l ), while ce is low and oe is at v i h . addresses are latched on the falling edge of we or ce , whichever hap- pens later. data is latched on the rising edge of the we or ce whichever occurs first. standard microprocessor write timings are used. refer to ac program character- istics and waveforms, figures 3, 8and13. command definitions device operations are selected by writing specific address and data sequences into the command register. table 3 defines these register command sequences. read/reset command the read or reset operation is initiated by writing the read/reset command sequence into the command regis- ter. microprocessor read cycles retrieve array data from the memory. the device remains enabled for reads until the command register contents are altered. the device will automatically power-up in the read/reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. the device will automatically power-up in the read/reset state. in this case, a com- mand sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value ensures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and figure 7 for the specific timing parameters. byte programing the device is programmed on a byte-byte basis. pro- gramming is a four bus cycle operation. there are two "unlock" write cycles. these are followed by the program table 1 ? bus operations operation ce oe we a0 a1 a9 i/o read l l h a 0 a 1 a 9 dout standby h x x x x x high z output disable l h h x x x high z write l h l a 0 a 1 a 9 d i n enable sector protect l v i d l x x v i d x verify sector protect l l h l h v i d code table 2 ? sector addresses table a16 a15 a14 address range sa0 0 0 0 00000h ? 03fffh sa1 0 0 1 04000h ? 07fffh sa2 0 1 0 08000h ? 0bfffh sa3 0 1 1 0c000h ? 0ffffh sa4 1 0 0 10000h ? 13fffh sa5 1 0 1 14000h ? 17fffh sa6 1 1 0 18000h ? 1bfffh sa7 1 1 1 1c000h ? 1ffffh
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 6 set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever occurs later, while the data is latched on the rising edge of ce or we whichever occurs first. the rising edge of ce or we begins programming. upon executing the pro- gram algorithm command sequence the system is not required to provide further controls or timings. the device will automatically provide adequate internally generated program pulses and verity the programmed cell status. the automatic programming operation is completed when the data on d 7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. the device requires a valid address be supplied by the sys- tem at this time. data polling must be performed at the memory location which is being programmed. programming is allowed in any address sequence and across sector boundaries. figure 3 illustrates the programming algorithm using typ- ical command strings and bus operations. chip erase chip erase is a six bus cycle operation. there are two 'unlock' write cycles. these are followed by writing the 'set-up' command. two more 'unlock' write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the erase algo- rithm (figure 4) sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data in d7 is "1" (see write operation status section - table 4) at which time the device returns to read the mode. see figures 4 and9. sector erase sector erase is a six bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "setup" command. two more "unlock" write cycles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data) is latched on the rising edge of we . a time-out of 100s from the rising edge of the last sector erase com- mand will initiate the sector erase command(s). multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase com- mand 30h to address in other sectors desired to be con- currently erased. a time-out of 100s from the rising edge of the we pulse for the last sector erase command will initiate the sector erase. if another sector erase command is written within the 100s time-out window the timer is reset. any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string. loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. when erasing a sector or sec- tors the remaining unselected sectors are not affected. the system is not required to provide any controls or tim- ings during these operations. data protection the act?f512k8 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transi- tions. during power up the device automatically resets the internal state machine in the read mode. also, with table 3 ? commands definitions command sequence bus write cycles first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle required addr data addr data addr data addr data addr data addr data read/reset 1 xxxh f0h read/reset 4 5555h aah 2aaah 55h 5555h f0h ra rd autoselect 4 5555h aah 2aaah 55h 5555h 90h byte program 6 5555h aah 2aaah 55h 5555h a0h pa pd chip erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h sector erase 6 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa 30h sector erase suspend erase can be suspended during sector erase with address (don?t care), data (b0h) sector erase resume erase can be resumed after suspend with address (don?t care), data (30h) notes : 1. address bit a15, a16, a17 and a18 = x = don't care. write sequences may be initiated with a15 in either state. 2. address bit a15, a16, a17 and a18 = x = don't care for all address commands except for program address (pa) and sector address ( sa). 3. ra = address of the memory location to be read pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a18, a17, a16 will uniquely select any sector. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we .
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 7 its control register architecture, alteration of the memory content only occurs after successful completion of spe- cific multi-bus cycle command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during vcc power-up and power-down, a write cycle is locked out for v c c less than 3.2v (typically 3.7v). if v c c aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 8 if data polling or the toggle bit indicates the device has been written with a valid erase command, d 3 may be used to determine if the sector erase timer window is still open. if d 3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent com- mands to the device will be ignored until the erase oper- ation is completed as indicated by data polling or toggle bit. if d 3 is low ("0"), the device will accept additional sector erase commands. to ensure the command has been accepted, the software should check the status of d 3 prior to and following each subsequent sector erase command. if d 3 were high on the second status check, the command may not have been accepted. see table 4 sector protection algorithims sector protection the act-f512k8 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. to activate this mode, the programming equipment must force v i d on control pin oe and address pin a 9 . the sector addresses should be set using higher address lines a 18 , a 17 , and a 16 . the protection mechanism begins on the falling edge of the we pulse and is terminated with the rising edge of the same. to verify programming of the protection circuitry, the pro- gramming equipment must force v i d on address pin a9 with ce and oe at v i l and we at v i h . scanning the sec- tor addresses (a 16 , a 17 , and a 18 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0,) will produce a logical "1" code at device output d 0 for a protected sector. otherwise the device will read 00h for unprotected sector. in this mode, the lower order addresses, except for 0, a1, and a6 are don't care. it is also possible to verify if a sector is protected during the sector protection operation. this is done by setting a6 = ce = oe = v i l and we = v i h (a 9 remains high at v i d ). reading the device at address location xxx2h, where the higher order addresses (a 18 , a 17 , and a 16 ) define a particular sector, will produce 01h at data out- puts (d0 - d7) for a protected sector. sector unprotect the act-f512k8 also features a sector unprotect mode, so that a protected sector may be unprotected to incor- porate any changes in the code. all sectors should be protected prior to unprotecting any sector. to activate this mode, the programming equipment must force vid on control pins oe , ce , and address pin a9. the address pins a 6 , a 16 , and a 12 should be set to v i h . the unprotection mechanism begins on the falling edge of the we pulse and is terminated with the rising edge of the same. it is also possible to determine if a sector is unprotected in the system by writing the autoselect command and a6 is set at v i h . performing a read operation at address location xxx2h, where the higher order addresses (a 18 , a 17 , and a 16 ) define a particular sector address, will pro- duce 00h at data outputs (d 0 -d 7 ) for an unprotected sector.
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 9 ce we oe data d 0 -d 7 t o e h t o e s d6=toggle d6 valid d6=toggle stop toggle d 0 -d 7 figure 1 ac waveforms for toggle bit during embedded algorithm operations i o l parameter typical units input pulse level 0 ? 3.0 v input rise and fall 5 ns input and output timing reference level 1.5 v output lead capacitance 50 pf notes: 1) v z is programmable from -2v to +7v. 2) i o l and i o h programmable from 0 to 16 ma. 3) tester impedance z o =75 w. 4) v z is typically the midpoint of v o h and v o l . 5) i o l and i o h are adjusted to simulate a typical resistance load circuit. 6) ate tester includes jig capacitance. i o h to device under test v z ~ 1.5 v (bipolar supply) current source current source c l = 50 pf figure 2 ac test circuit table 4 ? hardware sequence flags in progress status d 7 d 6 d 5 d 3 d 2 ? d 0 auto-programming d 7 toggle 0 0 d programming in auto erase 0 toggle 0 1 exceeding time limits auto-programming d 7 toggle 1 1 d programming in auto erase 0 toggle 1 1 note: (1) 1. d6 stops toggling (the device has completed the embedded operation)
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 10 figure 3 programming algorithm start write program command sequence data poll device last address increment address (see below) no yes programming complete 5555h/aah 2aaah/55h 5555h/a0h programming address/program data program command sequence (address/command): ? bus operations command sequence comments standby (1) write program valid address/data sequence read data polling to verify programming standby (1) compare data output to data expected note: 1. device is either powered-down, erase or program inhibit.
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 11 bus operations command sequence comments standby write program valid address/data sequence read data polling to verify programming standby compare data output to data expected figure 4 erase algorithm start erasure completed write erase command sequence (see below) data poll or toggle bit successfully completed chip erase command sequence (address/command) individual sector/multiple sector (address/command) erase command sequence 5555h/aah 2aaah/55h 5555h/80h 5555h/aah 2aaah/55h 5555h/10h 5555h/80h 5555h/aah 2aaah/55h 5555h/aah 2aaah/55h sector address/30h sector address/30h sector address/30h additional sector erase commands are optional
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 12 start read byte d 0 -d 7 address = va d 6 = toggle d 5 = 1 read byte d 0 -d 7 address = va fail pass yes no no yes no ? d 6 = toggle? (note 1) yes va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase figure 5 toggle bit algorithm start read byte d 0 -d 7 address = va d 7 = d 5 = 1 read byte d 0 -d 7 address = va fail pass yes no no yes no d 7 = data yes figure 6 data polling algorithm note 1. d 6 is rechecked even if d 5 = "1" because d 6 may stop toggling at the same time as d 5 changes to "1". note 1. d 7 is rechecked even if d 5 = "1" because d 7 may change simultaneously with d 5. va = byte address for programming = any of the sector addresses within the sector being erased during sector erase operation = xxxxh during chip erase ? ? ? toggle?
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 13 ac waveforms for read operations figure 7 t o h t c e t o e t a c c t r c t d f output valid high z high z outputs oe we ce addresses addresses stable we oe ce data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t o e t r c t c e t d f t o h t a h t a s t d h t w p h t w p t d s t c e t w c write/erase/program figure 8 operation, we controlled notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the deviced. 4. dout is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence. t g h w l
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 14 ac waveforms chip/sector figure 9 erase operations data addresses v c c 5555h data polling t a h ce t a s we 5555h 5555h sa 2aaah 2aaah t g h w l t w p t w p h t d s t d h t c e t v c e 55h aah 80h 55h 10h/30h aah oe notes: 1. sa is the sector address for sector erase. ac waveforms for data polling figure 10 during embedded algorithm operations t o e t c h t w h w h 1 or 2 t o e t o h t d f t c e t o e h * * dq7=valid data (the device has completed the embedded operation). dq0?dq6=invalid dq 7 dq 7= valid data dq0?dq6 valid data high z ce dq7 oe we dq0-dq6
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 15 start data = 01h set up sector address (a 18 , a 17 , a 16 ) figure 11 sector protection algorithm plscnt = 1 a 9 = v i d , ce = v i l oe = v i d activate we pulse time out 100s power down oe a9 should remain v i d ce = oe = v i h we = v i h address = sa, a 0 = 0, a 1 = 1, a 6 = 0 read from sector plscnt = 25 increment plscnt protect sector? another device failure remove v i d from a 9 write reset command sector protection complete yes yes no no no ? yes ?
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 16 sector unprotect algorithm figure 12 notes: sa0 = sector address for initial sector sa7 = sector address for last sector please refer to table 2 start data = 00h set up sector unprotect mode activate we pulse time out 10 msms start set a 1 = 1, a 0 = 0, a 6 = 1 setup sector address sa0 plscnt = 1000 address = sa7 sector device failure remove v i d from a 9 sector unprotect completed yes yes no protect all sectors plscnt = 1 a 12 = a 16 = v i h oe = ce = a 9 = v i d set set oe = ce = v i l a9 = v i d ? read data from device increment plscnt increment sector address no ? yes no ?
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 17 alternate ce controlled programming operation timings figure 13 we oe ce data addresses 5.0v 5555h pa data polling pa d7 d o u t pd aoh t w h w h 1 t a h t a s t d h t c p h t c p t d s t w s t w c t g h w l notes: 1. pa is the address of the memory location to be programmed. 2. pd is the data to be programmed at byte address. 3. d7 is the 0utput of the complement of the data written to the device. 4. d o u t is the output of the data written to the device. 5. figure indicates last two bus cycles of four bus cycle sequence.
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 18 pin numbers & functions 32 pins ? dip package 1 a 18 17 i/o 3 2 a 16 18 i/o 4 3 a 15 19 i/o 5 4 a 12 20 i/o 6 5\ a 7 21 i/o 7 6 a 6 22 cs 7 a 5 23 a 10 8 a 4 24 oe 9 a 3 25 a 11 10 a 2 26 a 9 11 a 1 27 a 8 12 a 0 28 a 13 13 i/o 0 29 a 14 14 i/o 1 30 a 17 15 i/o 2 31 we 16 v s s 32 v c c all dimensions in inches package outline "p4" ? .590" x 1.67" dip package 1.654 1.686 .100 .055 .020 .045 .016 .048 .019 .125 min .200 .145 .605 .580 .610 .590 .012 .009 typ pin 1 pin 32
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 19 pin numbers & functions 32 pins ? flat package 1 a 18 17 i/o 3 2 a 16 18 i/o 4 3 a 15 19 i/o 5 4 a 12 20 i/o 6 5 a 7 21 i/o 7 6 a 6 22 cs 7 a 5 23 a 10 8 a 4 24 oe 9 a 3 25 a 11 10 a 2 26 a 9 11 a 1 27 a 8 12 a 0 28 a 13 13 i/o 0 29 a 14 14 i/o 1 30 a 17 15 i/o 2 31 we 16 v s s 32 v c c all dimensions in inches package outline "f6" ? 32 lead, ceramic flat package .750 0.820 pin 1 .410 0.017 .010 .002 .125 max .005 pin 16 pin 17 pin 32 .005 (15 spaces at .050) 2 sides 0.400 min +.002 -.001
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 20 pin numbers & functions 32 pins ? flat package 1 a 18 17 i/o 3 2 a 16 18 i/o 4 3 a 15 19 i/o 5 4 a 12 20 i/o 6 5 a 7 21 i/o 7 6 a 6 22 cs 7 a 5 23 a 10 8 a 4 24 oe 9 a 3 25 a 11 10 a 2 26 a 9 11 a 1 27 a 8 12 a 0 28 a 13 13 i/o 0 29 a 14 14 i/o 1 30 a 17 15 i/o 2 31 we 16 v s s 32 v c c all dimensions in inches package outline "f7" ? 32 lead, ceramic flat package .750 0.820 pin 1 .410 0.017 .010 .002 pin 16 pin 17 pin 32 .005 (15 spaces at .050) 2 sides .030 typ 0 / -4 .125 .006 typ .132 max .025 typ .530 .005 seating plane .068 typ base plane max .005 +.002 -.001
aeroflex circuit technology scd1668 rev a 4/28/98 plainview ny (516) 694-6700 21 ordering information model number desc drawing number speed package act?f512k8n?150f6q 5962-9669201huc * 150 ns flat pack act?f512k8n?120f6q 5962-9669202huc* 120 ns flat pack act?f512k8n?090f6q 5962-9669203huc* 90 ns flat pack act?f512k8n?070f6q 5962-9669204huc* 70 ns flat pack act?f512k8n?060f6q 5962-9669205huc* 60ns flat pack act?f512k8n?150f7q 5962-9669201htc* 150 ns flat pack (formed) act?f512k8n?120f7q 5962-9669202htc* 120 ns flat pack (formed) act?f512k8n?090f7q 5962-9669203htc* 90 ns flat pack (formed) act?f512k8n?070f7q 5962-9669204htc* 70 ns flat pack (formed) act?f512k8n?060f7q 5962-9669205htc* 60ns flat pack (formed) act?f512k8n?150p4q 5962-9669201hxc* 150 ns dip pack act?f512k8n?120p4q 5962-9669202hxc* 120 ns dip pack act?f512k8n?090p4q 5962-9669203hxc* 90 ns dip pack act?f512k8n?070p4q 5962-9669204hxc* 70 ns dip pack act?f512k8n?060p4q 5962-9669205hxc* 60ns dip pack * pending circuit technology part number breakdown act? f 512k 8 n? 090 f6 q aeroflex circuit technology memory type f = flash eeprom memory depth options memory width, bits n = none memory speed, ns package type & size surface mount packages thru-hole packages f6 = .82" x .40" 32 lead fp unformed p4 = 32 pin dip f7 = .82" x .40" 32 lead fp formed c = commercial temp, 0c to +70c i = industrial temp, -40c to +85c t = military temp, -55c to +125c m = military temp, -55c to +125c, screening * q = mil-prf-38534 compliant / smd screening * screened to the individual test methods of mil-std-883 aeroflex circuit technology 35 south service road plainview new york 11830 telephone: (516) 694-6700 fax: (516) 694-6715 toll free inquiries: 1-(800) 843-1553 specifications subject to change without notice.

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